lx9_counter Project Status (08/22/2014 - 15:02:27)
Project File: lx9_countcrossing.xise Parser Errors: No Errors
Module Name: lx9_counter_test Implementation State: Programming File Generated
Target Device: xc6slx9-2csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
8 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 614 11,440 5%  
    Number used as Flip Flops 613      
    Number used as Latches 1      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 561 5,720 9%  
    Number used as logic 375 5,720 6%  
        Number using O6 output only 174      
        Number using O5 output only 185      
        Number using O5 and O6 16      
        Number used as ROM 0      
    Number used as Memory 98 1,440 6%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 98      
            Number using O6 output only 70      
            Number using O5 output only 0      
            Number using O5 and O6 28      
    Number used exclusively as route-thrus 88      
        Number with same-slice register load 77      
        Number with same-slice carry load 11      
        Number with other load 0      
Number of occupied Slices 204 1,430 14%  
Number of MUXCYs used 304 2,860 10%  
Number of LUT Flip Flop pairs used 655      
    Number with an unused Flip Flop 163 655 24%  
    Number with an unused LUT 94 655 14%  
    Number of fully used LUT-FF pairs 398 655 60%  
    Number of unique control sets 52      
    Number of slice register sites lost
        to control set restrictions
268 11,440 2%  
Number of bonded IOBs 4 200 2%  
    Number of LOCed IOBs 4 4 100%  
Number of RAMB16BWERs 3 32 9%  
Number of RAMB8BWERs 1 64 1%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 3 16 18%  
    Number used as BUFGs 3      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 0 200 0%  
Number of BSCANs 1 4 25%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.45      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Aug 22 15:01:36 201403 Warnings (0 new)1 Info (0 new)
Translation ReportCurrentFri Aug 22 15:01:43 2014001 Info (0 new)
Map ReportCurrentFri Aug 22 15:01:56 201403 Warnings (0 new)8 Infos (0 new)
Place and Route ReportCurrentFri Aug 22 15:02:07 2014000
Power Report     
Post-PAR Static Timing ReportCurrentFri Aug 22 15:02:14 2014003 Infos (0 new)
Bitgen ReportCurrentFri Aug 22 15:02:26 201402 Warnings (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrentFri Aug 22 15:02:26 2014

Date Generated: 08/22/2014 - 15:02:27