Avnet Spartan-6 LX9 Board: Or How ChipScope is your Saviour

I was recently working on a project which needed more gates than I had in my trusty current FPGA Board (Spartan3-200 on DLP-FPGA-HS). I quickly found the Avnet Spartan 6 LX9 board (AES-S6MB-LX9-G), which I could buy for $90 and have here in a few days. It also comes with a license for SDK for ChipScope, as it’s designed for experimenting with on-FPGA processors. It doesn’t have a full EDK license so you are a little limited in peripherals…

But for my project I didn’t care about that. I was however interested in ChipScope Pro, having used it previously at a job. This quick post will show you how valuable it can be – the license included with the LX9 board is “device locked” and will only work with XA6SLX9 parts. ChipScope Pro is not normally licensed as part of WebPack so the $90 board is a great deal when you consider the licensing cost.

My normal FPGA debugging, beyond Verilog testbenching, is to use a LogicPort on some spare IO lines. This works well – the LogicPort has a very high sampling rate (200MHz external, 500MHz internal). But it requires a physical connection, which requires a lot of IO pins. I was hoping ChipScope could eliminate this problem.

There is two cores of interest: the Integrated Logic Analyser (ILA) core, and the Virtual IO (VIO) core. They are both controlled by the Integrated Controller (ICON) core. You can only have one ICON, but it can control up to a number of ILA/VIO cores.

The VIO core gives you a virtual dashboard, where you can toggle bits and see results. This is pretty handy for validating/playing with cores to check they function as intended. Here I am checking a UART core from fpga4fun.com:


ChipScope Pro VIO

Note the VIO core doesn’t provide buffering, so data is transferred over the JTAG. This limits your polling speed of course, but makes it easy to play with things. It does let you define pulse trains or single pulses if you have special timing requirements on e.g.: load lines, as I had here.

The ILA core is strictly input. But it connects to BRAMs on-board the device, meaning you can buffer a fair amount of data. Since it’s all on-device the speed is basically limited by similar constraints to the rest of your design. Of course if you already have a packed chip you might not be able to spare any BRAMs…

Here I am debugging a state machine, note you how can even define ‘tokens’ so it decodes the states correctly:


ChipScope Pro ILA

 

So the combination of ChipScope ILA + VIO I’m hoping will make designs go by a lot faster.

Springer / SpringerLink MyCopy Review

Recently I was using an e-book I had access to through my school’s subscription to Springer. They advertised a ‘MyCopy’ service, which gives you a printed copy of the e-book for $25 including shipping http://www.springer.com/mycopy. I couldn’t find a review of the printing quality anywhere so though I’d post one quickly…

The actual copy would be $98 for softcover or $103 for hardcover. The trick with MyCopy is you can only order it assuming you have access to the e-book: thus you have a license to print a physical copy, and springer is just printing what you already are licensed for.

Anyway it looks good: colour wrap-around cover, B&W inside. Print quality is good – black is very “black”, although noticeably shiny. Paper seems bright and weight OK. As far as print on demand (POD) it’s great – better than I was expecting for $25. It’s lower quality than a real offset-print textbook, but it’s pretty close, better than other POD I’ve had. I recently bought a “real” book from the ‘Missing Manual’ series, which is apparently using POD for some books. The “real” book I got is far lower quality than the Springer MyCopy, so should give you some idea for comparison. The Springer MyCopy I got was printed in USA as well.

Some images (click for full resolution):

Front Cover:


MyCopy Example Cover

 

Binding Detail:


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Text close-up, white-looking areas are shiny reflections:


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Binding can be pushed down and lay somewhat flat without breaking:


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