Split Ground Plane: Example of failing high-speed signals


I’ve got a SASEBO-W board, which has a FPGA & a FT2232H for high-speed USB comms. I was seeing errors on the high-speed USB device, and couldn’t figure out why:


Power Split

The SASEBO-W is a multi-purpose board including a Xilinx LX150 Spartan 6 FPGA and a FTDI FT2232H USB interface. One use of the board is for measuring the power consumption of the FPGA and using that power consumption to perform power analysis attacks. I believe for this reason the ground planes are split, to facilitate making those measurements.

This split plane is joined through a common-mode choke. To use the high-speed USB interface it requires passing signals across a split in the plane – something very undesirable. The following figure shows what the ground currents for these signals would be. The signals are running on a 60 MHz clock if using the fastest available FT2232H mode.

A measurement of the potential difference between the two planes (done at CN3) shows the following figure. This is due to the 60 MHz clock being driven from the FT2232H to the FPGA, there was no data being transferred in this image.

Note that the FPGA I/O interface is 2.5V, meaning that signals being sent from the FPGA to the FT2232H will already have a reduced amplitude compared to the 3.3V I/O voltage. There should be enough headroom in practice such this interface works OK, and the FPGA has 3.3V tolerant I/Os.

The following figure shows a data bus line measured at the FT2232H in blue, the horizontal markers are set at 2.0V and 0.8V respectively, which are the limits for logic High/Low at the FT2232H. Note that due to this ground noise the signal is degraded to the point of crossing this threshold!

If we mount a jumper on CN3 this shorts the two ground planes together. This isn’t an ideal low-impedance path, but it will make an improvement. In the above figure the yellow line is with this jumper mounted.

The following figure shows the voltage difference between the two planes with such a jumper mounted. Compare to the earlier figure where the peak-to-peak voltage was almost 500mV!

Monitoring both the ground difference and bus lines show when the line switch there is still some extra noise contributed – the green line below (NB: note scale differs from above figure) shows a still fair amount of bounce during the transition, but in practice the USB communication seems reliable between the FT2232H and the FPGA.


So, that’s why you cannot cross high-speed traces across split planes!

1 thought on “Split Ground Plane: Example of failing high-speed signals”

  1. Pingback: FPGA Board Design Tips – Colin O’Flynn

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